I was in a chat with user @Mast on the Code Review Stack Exchange site (CR). @Mast, who is a Moderator there, then had a chat with our Moderator @SamGibson, and recommended I post this question for discussion.

I occasionally post comments on / questions here, suggesting that the OP consider posting the Verilog code also on the Code Review site. I do so under the following circumstances:

  • The question contains a detailed description of a Verilog simulation or synthesis problem.
  • The question has sufficient code to easily reproduce the problem.
  • There is at least one detailed answer providing a solution to the problem.
  • The Verilog code has other potential issues aside from the reported problem; the issues may either be functional or general coding style.

My comments are of the style: "If you are interested in a review of your code..."

Code reviews can often be verbose and stray far from the immediate problem reported by the OP. As such, I think supplementing an answer here with a review would be counter-productive because the solution could easily be buried in a lot of tangential review content. This is precisely the reason for the Code Review SE site (a site which is under-utilized in my opinion). People routinely refer questions from Stack Overflow to CR using comments.

To be clear, I am not referring to migrating the question. That is a different topic. I am referring to the OP posting a working version of the code on Code Review (as required on that site).

This isn't limited to just Verilog code, it's just that I happen to answer a lot of Verilog questions here. Code in any language would also apply.

@Mast saw one of my comments on an SO question, thereby leading to our chat. I mentioned that I thought most Verilog questions on SO and EE would benefit by a follow-up question on CR. This led @Mast to contact @Sam. And here we are. One question @Mast had for me was whether CR could handle any increase in Verilog questions. Given the small number of such questions here and on SO, it would be no problem even for a single person. It is worth mentioning that many people do not post a follow-up question on CR even if they like the idea.

If nothing comes of this discussion, I will continue posting the occasional comment. My referral comments are either well-received or ignored. So far, I have not had a negative response to one.

  • \$\begingroup\$ toolic - Hi, I appreciate you aren't proposing migrating Verilog questions from here to Code Review. I thought I had understood from what Mast said, what your suggestion was - but I don't see a specific proposal here. || Can you clarify what you propose would/could happen e.g. a rough list of steps? I think we would need that, for people to better understand what you suggest as the end point of this discussion. Although I think I know, it's best for you explain in case I misunderstood. So let's say someone asks a Verilog question here, what would be the next steps, as you see it? TY \$\endgroup\$
    – SamGibson Mod
    Mar 23 at 23:39
  • \$\begingroup\$ @SamGibson: it's pretty much my bullet list. I don't have any specific proposal for a referral mechanism other that a comment. I got the impression from Mast that you or he might have something more specific in mind, and that you both thought me posting a discussion here would lead to brainstorming. I'll try to update the question. Or, maybe Mast can chime in. \$\endgroup\$
    – toolic
    Mar 23 at 23:46
  • \$\begingroup\$ toolic - Re: "it's pretty much my bullet list" Ok, I see that as a list of your prerequisites. However (AIUC) it doesn't explain specific actions, nor who would do them, if those prerequisites are met. || If you're not planning to define that in the question then fine, I can say what I think could happen. However I didn't want to waste time explaining what I think you're proposing, in case I'm wrong :) || P.S. I also thought that Mast was suggesting to limit any process to just Verilog to begin with, as a pilot, rather than any language. || Do you want me to write a quick proposal? \$\endgroup\$
    – SamGibson Mod
    Mar 23 at 23:57
  • \$\begingroup\$ @SamGibson: Yes, limiting to just Verilog as a starting point would be fine. I just didn't want VHDL people or C people, etc., to feel left out :) I never had any mechanism in mind. My impression was that you Mods might, though. Yes, please write a proposal. \$\endgroup\$
    – toolic
    Mar 24 at 0:05
  • \$\begingroup\$ @SamGibson I did suggest starting out with just Verilog for the pilot, yes. The post here seems to be looking farther ahead, but I would consider anything beyond the Verilog pilot as a 'in case the idea takes off unexpectedly well, this is what it could lead to' presentation. A sketch for context, perhaps. \$\endgroup\$
    – Mast
    Mar 24 at 6:39
  • \$\begingroup\$ @Mast - Thanks for clarifying :) \$\endgroup\$
    – SamGibson Mod
    Mar 24 at 16:38

2 Answers 2


Here is a brain dump of how the process could work, if I understand you correctly. The idea is to make OPs more aware that an in-depth code review is available at Code Review.SE (that level of code review would not be on-topic nor desirable here on EE.SE). There are some aspects I have not solved or fully defined, but hopefully it's useful.


  • If a question included code (initially Verilog for the pilot), then once the on-topic question here has been answered and it meets those bullet points you listed above, then...

  • Someone (could be you or anyone else) can add a one-time short reminder comment on the question to remind the OP that if they want to, they can post their code on CR.SE for a deeper review, since their original question has been answered here on EE.SE.

Advantages for SE include:

  • SE overall is seen to be offering more than just "break/fix", especially since some OPs here may not know about CR.SE.

There may be advantages & disadvantages for CR.SE, but I'm not attempting to predict those here.

One possible disadvantage I see for EE.SE is the possibility to cause confusion for an OP, if they are sent a comment too soon suggesting that they use CR.SE, before their question here has been answered. They may go to CR.SE expecting a solution for non-working code and get frustrated when they are told not to ask that on CR.SE.

Some things to define would include:

  • A standard comment text, to keep a consistent message to OPs and avoid over- or under-selling what is available on CR.SE, as well as explaining how the OP should ask over there.

  • What would the process be and what would trigger someone leaving that sort of reminder comment on a question? If that reminder comment is left "too late" (TBD) then an OP may already have moved on and not be interested in using CR.SE for doing a code review (so it won't have added any value). But if that reminder comment is left "too early" (TBD) then it may muddy the water about what is happening here on EE.SE, if someone adds a comment suggesting an OP to post their code over at CR.SE (so it may cause confusion, as mentioned above).

My concern is how to get the timing right for when to suggest that site members here can add that comment on a question, explaining that further code review is available at CR.SE.

  • 2
    \$\begingroup\$ You nailed it!!! \$\endgroup\$
    – toolic
    Mar 24 at 10:08

It's hard not to notice that there are a limited number of questions on the relevant tags at the code review site, and for most of those, there is only one answer provided, and it's provided by you.

I have zero problems with a comment showing that there are valuable code-review services available at Code Review, that reviews at the level you'd find there are much more rigorous than what you'd be likely to find here, along with a guideline on how to post a good question there.

That said, I don't think people who ask verilog questions here are looking for that level of review.


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