The question In Xilinx Vivado, simulation mismatch between behavioral and post-synthesis implementations has been revised to cover now three different problems:
- critical synthesis warning on
temp_reg - inferred latch for
slow_reg - "noise present" on clock
The question has covered two points of Verilog that's poorly written (and almost-chaotically formatted) for correct synthesize and now wants to address a simulation issue that, given the user's comments, may be on refactored code.
The first answer, previously accepted, is now out of date. My answer, currently accepted, is also out of date. Effectively, this Q&A has turned into a one-OP-post forum for debugging the code. What should be done with this question?
Additional example: Verilog: Shift Register with feedback loop seems to have been repeatedly skipped in the First Posts review queue (by me included) so much that I've seen and skipped it again. Again, it's an HDL debugging question that seems to be developing as a moving target for answers.
