This was the question: Why does decreasing the voltage also decrease the circuit frequency?
It's a good question but was closed because "This question needs details or clarity". So I added details. My edit was rejected because "This edit deviates from the original intent of the post".
This is not true. I just added more details and context to make the question clear and save it. All I did was added the definitions of terms which were already present in the question. Without my edit, the post lacks context. All it states is
Keeping the same clock frequency becomes unsustainable as Vdd is continuously reduced, because the rise and fall times of signals stop meeting the noise margin of the gate.
Other users who are not familiar with this field will have no idea what voltage Vdd refers to here.
So I added
Here, Vdd is the supply voltage of the CMOS gate. Noise margin of the gate is the allowable noise voltage on the inputs of the gate such that the output will not get corrupted. Rise time is the time taken for the output signal of the gate to rise from 10% to 90% of its final voltage value of logic High level. Fall time is the time taken for the output signal to fall from 90% to 10% of its final voltage value for logic Low level.
And slightly modified the last statement to
I don't understand why rise time and fall time increases as voltage Vdd decreases.