Verilog is a C-like language. It uses a similar layout, has equivalent control keywords, and highlights OK when using the C syntax highlighter:
Of course, it has some notable differences, including many more keywords, especially the
end keywords as opposed to curly braces, and various syntactic incompatibilities like
At the moment, I've set up the syntax highlighter to use
lang-c to highlight Verilog. In my opinion, it's often better than nothing:
but it's not great. For example,
' is used in places it's not used in C, causing stuff like:
' in code, but the highlighter assumes that it's a character delimiter.
Would you rather have
Please report any major highlighting mistakes,
and use Broken, see lang-none specifier only works in preview.
<!-- language: lang-none --> to prefix any code blocks that you don't want syntax highlighted.