# Do we need a custom Verilog syntax highlighter?

Verilog is a C-like language. It uses a similar layout, has equivalent control keywords, and highlights OK when using the C syntax highlighter:

Of course, it has some notable differences, including many more keywords, especially the begin and end keywords as opposed to curly braces, and various syntactic incompatibilities like @ and '.

At the moment, I've set up the syntax highlighter to use lang-c to highlight Verilog. In my opinion, it's often better than nothing:

but it's not great. For example, ' is used in places it's not used in C, causing stuff like:

Verilog uses ' in code, but the highlighter assumes that it's a character delimiter.

Would you rather have lang-c or nothing? How important would a custom highlighter be? There are currently only 29 questions with the tag, is this important enough to make all the visitors download a couple hundred bytes of Javascript?

Please report any major highlighting mistakes, and use <!-- language: lang-none --> to prefix any code blocks that you don't want syntax highlighted. Broken, see lang-none specifier only works in preview.