4
\$\begingroup\$

Please add the same syntax highlighting as the tag to the tag for consistency. Currently, verilog has syntax highlighting, but system-verilog does not. The system-verilog tag info aptly states that it "is a backwards-compatible superset of verilog". Thus, it makes sense for both to use the same highlighting.

Several questions are tagged with both, and the highlighting looks fine. For example, this question.

\$\endgroup\$
1
\$\begingroup\$

Sorry for the delay on this one.

To answer your question, yes, I have found where I could change the syntax highlighter for the system-verilog tag (currently none), to match the verilog tag highlighting.

However as kindly explained in this answer from MarkU, the syntax highlighting module being used for the verilog tag is called "lang-vhdl". There is no syntax highlighter specifically for Verilog (or System Verilog) available for me to choose. (The SE decision not to include Verilog & System Verilog highlighting in the SE-specific highlight.js is stated here.)

Before my upvote for usefulness, that answer from MarkU had 1 downvote and 0 upvotes (and no explanatory comment for the downvote) - so was the original downvote to that answer, because there is some big negative consequence to the proposed change which no-one else has mentioned?

Summary:

I believe I can make the change you requested, but the downvote on that answer pointing out that it will invoke the lang-vhdl highlighting, is puzzling. Further feedback would be helpful.

\$\endgroup\$
8
  • \$\begingroup\$ Thanks for the reply. I understand you mods are very busy. Yes, I understand the verilog tag currently uses vhdl highlighting. Someone else long ago must've decided the vhdl highlighting was good enough for verilog, too; I agree with that, and I assume the rest of the users here have had no problem with it over the years. Regrading the other 2 answers, they seem to have taken this simple request off onto other tangents, unfortunately. I intentionally kept my request brief in my Question. Since the Question has only upvotes, no one strongly disagrees with the request.... \$\endgroup\$
    – toolic
    Oct 7 at 23:42
  • \$\begingroup\$ ... Shall I update the Question with more details? I think it would be beneficial for the verilog and system-verilog tags to be consistent with each other regarding highlighting. My request is that you make the change since only Moderators can make this change. \$\endgroup\$
    – toolic
    Oct 7 at 23:42
  • \$\begingroup\$ @toolic - Hi, I don't think more details are needed in the question - if lang-vhdl syntax highlighting is as good as we can get (and it will match the verilog tag behaviour) then I can enable that same syntax highlighting on the system-verilog tag now. OK? \$\endgroup\$
    – SamGibson Mod
    Oct 7 at 23:51
  • \$\begingroup\$ Yes, please do enable the same highlighting. I think it's good enough. \$\endgroup\$
    – toolic
    Oct 7 at 23:55
  • \$\begingroup\$ @toolic - OK, I've now enabled that. I can now see some (limited) highlighting on a couple of SV questions I just checked. Can you please look at some SV questions and confirm that (some) syntax highlighting is working for you too? Thanks. \$\endgroup\$
    – SamGibson Mod
    Oct 8 at 0:00
  • \$\begingroup\$ I looked at a few SV-only posts with code, and they have syntax highlighting look as expected. Thanks once again. \$\endgroup\$
    – toolic
    Oct 8 at 0:04
  • \$\begingroup\$ @toolic - Great, thanks for your help, I'll consider this topic resolved. Could you please accept this answer if you agree? And sorry again for the delay. Sincere regards... \$\endgroup\$
    – SamGibson Mod
    Oct 8 at 0:06
  • 1
    \$\begingroup\$ Accepted!!!!!!! \$\endgroup\$
    – toolic
    Oct 8 at 0:06
0
\$\begingroup\$

Some notes:

As of 2020-09-24, all stack exchange sites use highlight.js for code-formatting and syntax-highlighting, see Goodbye, Prettify. Hello highlight.js! Swapping out our Syntax Highlighter

The list of languages supported by highlight.js is at https://github.com/highlightjs/highlight.js/blob/main/SUPPORTED_LANGUAGES.md and verilog and VHDL are both on the list.

For some strange reason, tag is configured to use the lang-vhdl highlighter:

https://electronics.stackexchange.com/tags/verilog/info
Code Language (used for syntax highlighting): lang-vhdl

I don't know why. The highlight.js posted on github has separate options for verilog and vhdl, but stackoverflow What is syntax highlighting and how does it work? mentions that they use their own fork of this library, and don't have all of the modules installed. At any rate, if the lang-vhdl highlighter is working well enough for verilog, I suppose it would work for system verilog just as well, right?

Is it possible for one of our local site moderators to edit the tag's Code Language field to match the verilog and vhdl tags (i.e. lang-vhdl)? Or is this something that requires the whole meta feature-request route to the stackexchange community managers?

\$\endgroup\$
1
  • \$\begingroup\$ MarkU - Hi, I don't know if you're following this question, so this comment is just to mention that I've added an answer which builds on yours. Yes, I could change that highlighting for the system-verilog tag to match the verilog tag (without needing to involve the CMs, as far as I can tell). But the downvote on your answer is puzzling, and I wonder if that is someone indicating a flaw in that plan that we haven't spotted :-( Feedback on my answer is welcome. Thanks. \$\endgroup\$
    – SamGibson Mod
    Oct 7 at 23:34
0
\$\begingroup\$

One other (labor-intensive) way to mitigate this lack of code highlighting for questions tagged but not would be to edit each question so that its code blocks are introduced with

```verilog (whatever highlighter tag uses)

or

```lang-verilog (use verilog highlighter, regardless of the tag default highlighter)

instead of just ``` (which uses the tag default highlighter).

Just trying that out here, maybe the syntax highlighting doesn't work on meta?

# example code using default highlighter
module abc(input net d, output reg e)
assign e = d
endmodule
-- example code using lang-vhdl
module abc(input net d, output reg e)
assign e = d
endmodule
# example code using lang-verilog
module abc(input net d, output reg e)
assign e = d
endmodule
-- example code using same highlighting as tag:vhdl
module abc(input net d, output reg e)
assign e = d
endmodule
# example code using same highlighting as tag:verilog
module abc(input net d, output reg e)
assign e = d
endmodule
# example code using same highlighting as tag:system-verilog
module abc(input net d, output reg e)
assign e = d
endmodule
\$\endgroup\$

You must log in to answer this question.

Not the answer you're looking for? Browse other questions tagged .