One other (labor-intensive) way to mitigate this lack of code highlighting for questions tagged system-verilog but not verilog would be to edit each question so that its code blocks are introduced with
```verilog
(whatever highlighter tag verilog uses)
or
```lang-verilog
(use verilog highlighter, regardless of the tag default highlighter)
instead of just ```
(which uses the tag default highlighter).
Just trying that out here, maybe the syntax highlighting doesn't work on meta?
# example code using default highlighter
module abc(input net d, output reg e)
assign e = d
endmodule
-- example code using lang-vhdl
module abc(input net d, output reg e)
assign e = d
endmodule
# example code using lang-verilog
module abc(input net d, output reg e)
assign e = d
endmodule
-- example code using same highlighting as tag:vhdl
module abc(input net d, output reg e)
assign e = d
endmodule
# example code using same highlighting as tag:verilog
module abc(input net d, output reg e)
assign e = d
endmodule
# example code using same highlighting as tag:system-verilog
module abc(input net d, output reg e)
assign e = d
endmodule