Questions tagged [syntax-highlighting]

This cite uses an automatic for matter for code. For example VHDL. Questions about it belong here.

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4
votes
3answers
81 views

Add syntax highlighting for the system-verilog tag

Please add the same syntax highlighting as the verilog tag to the system-verilog tag for consistency. Currently, verilog has syntax highlighting, but ...
10
votes
2answers
323 views

Wasting a tag to properly format code

I just added a "c" tag to make sure the code blocks are properly shown. STM32 Sleep Mode: Interrupt gets executed but the CPU stays in WFI. In this case, there was plenty of room for tags, but in ...
3
votes
0answers
78 views

Assembly and Basic syntax highlighting

I request the feature of syntax highlighting Assembly and Basic code. As W5VO said, we don't have it yet. However, Assembly is used regularly on this site. And while we're at it, why not add Basic as ...
16
votes
1answer
245 views

Support VHDL syntax highlighting

We now have syntax highlighting for a host of languages through Google Prettify. Regrettably, the default set: ...
4
votes
1answer
42 views

lang-none specifier only works in preview

This question uses an ASCII diagram and has the verilog tag. To avoid syntax highlighting, I used the <!-- language: lang-none --> directive. Per the SO ...
7
votes
0answers
218 views

Do we need a custom Verilog syntax highlighter?

Verilog is a C-like language. It uses a similar layout, has equivalent control keywords, and highlights OK when using the C syntax highlighter: Of course, it has some notable differences, including ...
8
votes
1answer
115 views

Syntax highlighting should be supported on Electrical Engineering, like on SO

I thought based on this MSO question, it might be that syntax highlighting is supported here, as people rarely tag their questions with the appropriate language, so the highlighter might go into "null-...