Electrical Engineering
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Tim's user avatar
Tim's user avatar
Tim
  • Member for 11 years, 4 months
  • Last seen more than 9 years ago
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About

Professional ASIC engineer with experience in RTL design, Verilog, synthesis, power, and timing issues on billion+ gate ICs.

Other hobbies include:

  • Computer Graphics
  • Android Programming
  • C++ Programming

Personal released projects:

Portfolio Map-----------Electron Flux

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All Questions Answers
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question
5
CircuitLab plugin doesn't load for me in latest Firefox
Apr 20, 2013
answer
3
Time limit before edits commit to revision history
Apr 3, 2013
Top network posts
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163
Is there a command in Vim/Vi to move the cursor to the end of a search highlight?
73
Is glm::ortho() actually wrong?
61
set the texture for by glUniform1i
59
How to find replace using regex groups in vim
51
Why FloatBuffer instead of float[]?

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