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Tim's user avatar
Tim
  • Member for 11 years, 10 months
  • Last seen more than 9 years ago
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About

Professional ASIC engineer with experience in RTL design, Verilog, synthesis, power, and timing issues on billion+ gate ICs.

Other hobbies include:

  • Computer Graphics
  • Android Programming
  • C++ Programming

Personal released projects:

Portfolio Map-----------Electron Flux

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