Electronic engineer by training, hacker (in the old-fashioned sense) by inclination. Particularly good with embedded software and FPGAs
I'm currently an engineer at Conekt - which is a part of ZF Race Engineering - but all opinions expressed here are my own, not necessarily ZF's. And possibly not even mine if I'm playing devil's advocate.
Top network posts
- 29 Clarification on Ethernet, MII, SGMII, RGMII and PHY
- 28 Experiences with Test Driven Development (TDD) for logic (chip) design in Verilog or VHDL
- 24 Reverse bit order on VHDL
- 24 VHDL - How should I create a clock in a testbench?
- 24 How to sub with matched groups and variables in Python
- 24 shift a std_logic_vector of n bit to right or left
- 23 When must a signal be inserted into the sensitivity list of a process
- View more network posts →