Electrical Engineering
user avatar
user avatar
user avatar
toolic
  • Member for 7 years, 2 months
  • Last seen this week
Profile Activity
Stats
2,630
reputation
329
reached
1
answer
2
questions
Communities
About

Testbench 101

Perl Basic debugging checklist

Badges
View all badges
This user doesn’t have any gold badges yet.
8
silver badges
8
bronze badges
Top tags
7
Score
1
Posts
33
Posts %
0
Score
2
Posts
67
Posts %
0
Score
1
Posts
33
Posts %
0
Score
1
Posts
33
Posts %
0
Score
1
Posts
33
Posts %
Top posts
All Questions Answers
Score Newest
answer
7
Can I ask about societal topics related to EE?
Oct 22, 2021
question
6
Would a Moderator delete the misspelled [verliog] tag?
Nov 26, 2021
question
4
Add syntax highlighting for the system-verilog tag
Sep 15, 2021
Top network posts
View all network posts
65
How can I tell if a Perl module is core or part of the standard install?
58
How can I output a die() message without the location information?
45
What do curly braces mean in Verilog?
40
What is the difference between == and === in Verilog?
38
ADDRESS WIDTH from RAM DEPTH

Your privacy

By clicking “Accept all cookies”, you agree Stack Exchange can store cookies on your device and disclose information in accordance with our Cookie Policy.